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Audio Codec with Embedded SigmaDSP(R) Processor ADAV400
FEATURES
Fully programmable audio digital signal processing (DSP) for enhanced sound processing Scalable digital audio delay line Pool of 400 ms @ 48 kHz (200 ms for stereo channel) High performance, integrated analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) 1 stereo analog input (ADC) 4 stereo analog inputs with mux-to-stereo ADC 4 stereo (8-channel) analog outputs (DACs) Dedicated headphone output with integrated amplifier Multichannel digital I/O 8-channel I2S input and output modes 8- and 16-channel TDM input and output modes 2-channel (1 stereo) asynchronous I2S input with integrated sample rate converter (SRC), supporting sample rates from 5 kHz to 50 kHz Features SigmaStudioTM, a proprietary graphical programming tool for fast development of custom signal flows Includes various third-party audio algorithms I2C(R) control interface Operates from 3.3 V (analog), 1.8 V (digital core), 3.3 V (digital interface) Features on-chip regulator for single 3.3 V operation 80-lead LQFP package (14 mm x 14 mm) Temperature range: 0C to 70C
APPLICATIONS
ATV and AV audio applications TV audio processing Set top box (STB) HTiB General audio enhancement
FUNCTIONAL BLOCK DIAGRAM
ADAV400
MULTICHANNEL DIGITAL OUTPUTS SDO0 SDO1 SDO2 SDO3 LRCLK1 PROGRAMMABLE AUDIO PROCESSOR CORE BCLK1 VOUT1 VOUT2 DAC VOUT3 VOUT4 DAC HPOUTL HPOUTR AUXL1 AUXR1 A-V SYNC DELAY MEMORY DAC AUXL2 AUXR2
05811-001
MCLKI MCLKO SCL SDA AD0 BCLK0 LRCLK0
PLL
SYSTEM CLOCKS
I2C INTERFACE
DAC
SRC ASYNCHRONIZE DIGITAL INPUT
SDIN0 SDIN1 SDIN2 SDIN3 AINL1 AINR1 AINL4 AINR4 ADC SYNCHRONIZE MULTICHANNEL DIGITAL INPUT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
ADAV400 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Digital Timing............................................................................... 6 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 13 Analog Inputs.............................................................................. 13 Sample Rate Converter Block ................................................... 13 PLL Block..................................................................................... 13 Analog Outputs........................................................................... 13 Headphone Amplifier ................................................................ 14 Voltage Regulator ....................................................................... 14 Control Port..................................................................................... 15 I2C Port ........................................................................................ 15 Signal Processing ............................................................................ 18 Numeric Formats........................................................................ 18 Programming .............................................................................. 18 RAMs and Registers....................................................................... 19 Control Port Addressing ........................................................... 19 Parameter RAM Contents......................................................... 19 Recommended Program/Parameter Loading Procedures.... 20 Target/Slew RAM ....................................................................... 20 Safeload Registers ....................................................................... 23 Data Capture Registers .............................................................. 23 Control Port Read/Write Data Formats .................................. 24 Serial Data Input/Output Ports .................................................... 26 Control Registers ............................................................................ 28 Audio Core Control Register .................................................... 31 RAM Modulo Control Register................................................ 32 Serial Output Control Registers ............................................... 32 Serial Input Control Register .................................................... 32 SRC Serial Port Control Register ............................................. 33 ADC Input Mux Register .......................................................... 33 Power Control Register ............................................................. 33 User Control Register 2 ............................................................. 33 User Control Register 1 ............................................................. 33 DAC Amplifier Register ............................................................ 33 Typical Application Diagram.................................................... 34 Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35
REVISION HISTORY
1/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADAV400 GENERAL DESCRIPTION
The ADAV400 is an enhanced audio processor. Integrating high performance analog and digital I/Os with a powerful, audiospecific, programmable core enables designers to differentiate their products through audio performance. The audio processing core is based on Analog Devices SigmaDSP technology featuring full 28-bit processing (56-bit in double precision mode), a sophisticated, fully programmable dynamics processor, and delay memory. This technology allows the system designer to compensate for real world limitations of speakers, amplifiers, and listening environments. This compensation results in a dramatic improvement of the perceived audio quality through speaker equalization, multiband compression and limiting, and thirdparty-branded algorithms. The analog I/O integrates Analog Devices proprietary continuous time, multibit, sigma-delta (-) architecture. This integration brings a higher level of performance to systems that are required to meet system branding certification by third-party algorithm providers. The analog inputs feature a 95 dB dynamic range stereo ADC fed from a four-stereo input mux. The four stereo analog outputs are each driven by a 95 dB dynamic range DAC. A dedicated headphone channel is included with integrated amplifiers. The ADAV400 supports multichannel digital inputs and outputs. An integrated SRC on one channel provides the capability to support any input sample rate in the range 5 kHz to 50 kHz, synchronizing this input to the internal DSP engine. The ADAV400 is supported by a powerful graphical programming tool that includes blocks such as general filters, EQ filters, dynamics processing, mixers, volume, and third-party algorithms for fast development of custom signal flows.
Rev. 0 | Page 3 of 36
ADAV400 SPECIFICATIONS
AVDDn 1 = 3.3 V, ODVDD = 3.3 V, DVDD = internal voltage regulator, temperature = 0C to 70C, master clock = 12.288 MHz, measurement bandwidth = 20 Hz to 20 kHz, ADC input signal = 1 kHz, DAC output signal = 1 kHz, unless otherwise noted. Table 1.
Parameter REFERENCE SECTION Absolute Voltage VREF VREF Temperature Coefficient ANALOG INPUTS (SINGLE-ENDED) Number of Channels Full-Scale Analog Input DC Offset ADC SECTION Resolution Dynamic Range A-Weighted Total Harmonic Distortion + Noise Interchannel Gain Mismatch Crosstalk Gain Error Power Supply Rejection ADC DIGITAL DECIMATOR FILTER CHARACTERISTICS @ 48 kHz 2 Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC OUTPUTS (SINGLE-ENDED) Number of Channels Resolution Full-Scale Analog Output Dynamic Range A-Weighted Total Harmonic Distortion + Noise 3 Crosstalk Gain Error Interchannel Gain Mismatch DC Offset Power Supply Rejection DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS @ 48 kHz2 Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Min Typ 1.5 130 8 100 10 24 90 95 -93 0.1 -78 -6 -83 Max Unit V ppm/C Four stereo input channels 2 V rms input with 20 k series resistor Relative to VREF Stereo ADC Test Conditions/Comments
A rms mV Bits dB dB dB dB % dB
-60 dB with respect to full-scale analog input -3 dB with respect to full-scale analog input Left and right channel gain mismatch Analog channel crosstalk (AINYm1 to AINYm1) One channel = -3 dB, other channel = 0 V 1 kHz, 300 mV p-p signal at AVDDn1
22.5 0.0002 24 26.5 100 1040 8 24 1 90 95 -90 -100 5 0.1 1 -87
kHz dB kHz kHz dB s DAC amplifier register contents = 0x0010 Four stereo output channels Bits V rms dB dB dB % dB mV dB -60 dB with respect to full-scale code input -3 dB with respect to full-scale code input Analog channel crosstalk (VOUTm1 to VOUTm1) One channel = -3 dB, other channels = 0 V Left and right channel gain mismatch Relative to VREF 1 kHz, 300 mV p-p signal at AVDDn1
21.769 0.01 23.95 26.122 75 580
kHz dB kHz kHz dB s
Rev. 0 | Page 4 of 36
ADAV400
Parameter HEADPHONE OUTPUT (SINGLE-ENDED) Number of Channels Resolution Full-Scale Analog Output Dynamic Range A-Weighted Total Harmonic Distortion + Noise Gain Error Interchannel Gain Mismatch DC Offset Power Supply Rejection PLL SECTION2 Master Clock Input (MCLKI) SRC2 Dynamic Range A-Weighted Total Harmonic Distortion + Noise Sample Rate DIGITAL INPUT/OUTPUT Input Voltage High (VIH) Input Voltage Low (VIL) Input Leakage (IIH @ VIH = ODVDD) Input Leakage (IIL @ VIL = 0 V) Output Voltage High (VOH @ IOH = 0.4 mA) Output Voltage Low (VOL @ IOL = -3.2 mA) Input Capacitance SUPPLIES Analog Supplies AVDDn1 Digital Supplies DVDD Interface Supply ODVDD Supply Current, Normal Mode Analog Current (AVDD1) Digital and Interface Current PLL Current Supply Current, Power-Down Mode Analog Current Digital and Interface Current PLL Current
1 2
Min
Typ
Max
Unit
2 24 1 92 -84 4 0.5 -30 -84 64 x fS 512 x fS
Test Conditions/Comments Measured at headphone output with 32 load, headphone amplifier register contents = 0x0001 One stereo channel
Bits V rms dB dB % dB mV dB MHz -60 dBFS with respect to full-scale code input -3 dBFS with respect to full-scale code input
Relative to VREF 1 kHz, 300 mV p-p signal at AVDDn1
115 -113 5 2.0 50 ODVDD 0.8 10
dB dB kHz V V A A V
-60 dBFS input (worst-case input fS = 50 kHz) 0 dBFS input (worst-case input fS = 50 kHz)
-60 2.4 0.4 10 3.15 1.6 3.15 3.30 1.8 3.30 90 120 5 6 1.5 5 3.45 2.0 3.45 110 135 6 8.5 6 50
V pF V V V mA mA mA mA mA A MCLK = 12.288 MHz, ADCs and DACs active, headphone outputs active and driving a 32 load, Power control register = 0xFFFF RESET low, MCLK = 3.074 MHz, AINx = AGND, DAC and headphone outputs floating
The n refers to supply number, the m refers to channel number, and the Y refers to stereo channel identifier: L for left channel or R for right channel. Guaranteed by design. 3 Measured on one DAC with other DACs and ADCs off.
Rev. 0 | Page 5 of 36
ADAV400
DIGITAL TIMING
Table 2.
Parameter MASTER CLOCK AND RESET fMCLKI (MCLKI Frequency) tMCH (MCLKI High) tMCL (MCLKI Low) tRLPW (RESET Low Pulse Width) I2C PORT fSCL (SCL Clock Frequency) tSCLH (SCL High) tSCLL (SCL Low) Start Condition tSCS (Setup Time) tSCH (Hold Time) tDS (Data Setup Time) tSCR (SCL Rise Time) tSCF (SCL Fall Time) tSDR (SDA Rise Time) tSDF (SDA Fall Time) Stop Condition tSCSH (Setup Time) SERIAL PORTS Slave Mode tSBH (BCLKx High) tSBL (BCLKx Low) fSBF (BCLKx Frequency) tSLS (LRCLKx Setup) tSLH (LRCLKx Hold) tSDS (SDINx Setup) tSDH (SDINx Hold) tSDD (SDOx Delay) Master Mode tMLD (LRCLKx Delay) tMDD (SDOx Delay) tMDS (SDINx Setup) tMDH (SDINx Hold) Min 3.024 10 10 20 Max 24.576 Unit MHz ns ns ns kHz s s s s ns ns ns ns ns s Relevant for repeated start condition The first clock is generated after this period Comments
400 0.6 1.3 0.6 0.6 100 300 300 300 300 0.6
40 40 64 x fS 10 10 10 10 40 5 40 10 10
ns ns ns ns ns ns ns ns ns ns ns To BCLK rising edge From BCLK rising edge To BCLK rising edge From BCLK rising edge From BCLK falling edge From BCLK falling edge From BCLK falling edge From BCLK rising edge From BCLK rising edge
Rev. 0 | Page 6 of 36
ADAV400
Digital Timing Diagrams
tSBH
BCLKx
tSBL tSLH
LRCLKx
tSLH
SDINx LEFT-JUSTIFIED MODE
tSDS
MSB
tSDH
MSB - 1
SDOx I2S MODE
MSB
tMDD tSDD
Figure 2. Serial Port Timing
tSCH
SDA
tSDR
tDS
tSCH
tSDF
tSCR
SCL
tSCLH
tSCLL
tSCF
tSCS
tSCSH
Figure 3. I2C Port Timing
tMP
MCLK
05811-004
Figure 4. Master Clock Timing
Rev. 0 | Page 7 of 36
05811-003
05811-002
ADAV400 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter DVDD to DGND ODVDD to DGND AVDD to AGND AGND to DGND Digital Inputs Analog Inputs Reference Voltage Soldering (10 sec) Rating 0 V to 2.2 V 0 V to 4.0 V 0 V to 4.0 V -0.3 V to +0.3 V DGND - 0.3 V to ODVDD + 0.3 V AGND - 0.3 V to ADVDD + 0.3 V Indefinite short-circuit to ground 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 8 of 36
ADAV400 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
FILTA 1 VREF 2 AGND 3 AVDD1 4 NC 5 NC 6 NC 7 NC 8 NC 9 NC 10 NC 11 NC 12 DGND 13 DVDD 14 AD0 15 SDA 16 SCL 17 TEST0 18 TEST1 19 DGND 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN 1
VOUT4
AUXR2
AVDD5
AVDD4
AUXL2
TEST2
AINR4
AINR3
AINR2
AINR1
AGND
AGND
AINL4
AINL3
AINL2
AINL1
FILTD
IDAC
NC
NC
60 59 58 57 56 55
VOUT3 VOUT2 VOUT1 AUXR1 AUXL1 AVDD3 HPOUTR HPOUTL AGND AGND PLL_LF AVDD2 DGND DVDD RESET NC NC SDO3 SDO2 DGND
ADAV400
TOP VIEW (Not to Scale)
54 53 52 51 50 49 48 47 46 45 44 43 42 41
SDO0
MCLKI
LRCLK0
VDRIVE
MCLKO
SDIN0
SDIN1
SDIN2
SDIN3
LRCLK1
ODVDD
SDO1
DGND
DGND
DVDD
DVDD
NC
BCLK0
BCLK1
DVDD
NC = NO CONNECT
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 to 12, 65, 66 13, 20, 28, 32, 41, 48 14, 21, 31, 40, 47 15 16 17 18 19 22 to 25 26 27 29 30 Mnemonic FILTA VREF AGND AVDD1 NC DGND I/O O Description ADC Filter Decoupling Node for the ADC. Decouple this pin to AGND (Pin 3). Voltage Reference. This pin is driven by an internal 1.5 V reference voltage. Decouple this pin to AGND (Pin 3) ADC Ground. Connect this pin to the analog ground plane. Analog Power Supply Pin for the ADC. Connect this pin to 3.3 V and decouple to AGND (Pin 3) Not Connected Internally. Digital Ground. Connect this pin to the digital ground plane.
DVDD
Digital Power Supply Pins. Connect these pins to 1.8 V, either directly or by using the on-chip regulator. Decouple to DGND I I/O I I2C Address Select. Tie to ODVDD for address 0x28 (write) and 0x29 (read) or DGND for address 0x2A (write) and 0x2B (read) Serial Data Input/Output for the I2C Control Port. Serial Clock for the I2C Control Port. Test Pin. Connect to ODVDD. Test Pin. Connect to ODVDD. Serial Data Inputs. BCLK1 and LRCLK1 are used as the timing signals for SDIN0 to SDIN3. Left/Right Clock for Sample Rate Converter (SRC). This input frame synchronization signal is associated with SDIN0 to SDIN3 when one of these input channels is redirected to the SRC. Bit Clock for Sample Rate Converter (SRC). This input clock is associated with SDIN0 to SDIN3 when one of these input channels is redirected to the SRC. Digital Interface Supply (3.3 V) Pin. Connect this pin to a 3.3 V digital supply. Decouple to DGND. Drive for External PNP Transistor. This is used with the on-chip 1.8 V regulator circuit
Rev. 0 | Page 9 of 36
AD0 SDA SCL TEST0 TEST1 SDIN [0:3] LRCLK0 BCLK0 ODVDD VDRIVE
I I I
05811-005
ADAV400
Pin No. 33 34 35 Mnemonic MCLKI MCLKO BCLK1 I/O I O I/O Description Master Clock Input. The ADAV400 uses a phase-locked loop (PLL) to generate all of the appropriate internal clock for the DSP core. Audio Clock Output. The MCLKO pin can be programmed to output the internal audio clock. Bit Clock for Serial Data Input/Output. This clock and the LRCLK1 are used as clock and frame sync signals for the SDINx and SDOx pins. These clocks are inputs to the ADAV400 when the port is configured as a slave, and outputs when the port is configured as a master. On power up, these pins are set to slave mode to avoid conflicts with external master mode devices. Left/Right Clock for Serial Data Input/Output. This clock and the BCLK1 are used as clock and frame sync signals for the SDINx and SDOx pins. Serial Data Outputs. These pins should be left unconnected. I Active Low Reset Signal. After RESET the ADAV400 is powered down. Analog Power Supply Pin for the PLL. Connect this pin to 3.3 V and decouple to AGND (Pin 51). PLL Loop Filter. External components are required to allow the PLL to function correctly. See the PLL Block section for details of these components. PLL Ground. Connect this pin to the analog ground plane. Headphone Driver Ground. Connect this pin to the analog ground plane. Left Headphone Output. Analog output from the headphone amplifiers. Right Headphone Output. Analog output from the headphone amplifiers. Analog Power Supply Pin for the headphone amplifier. Connect this pin to 3.3 V and decouple to AGND (Pin 52). Auxiliary Analog Output Left 1 Auxiliary Analog Output Right 1. Main Analog Output 1 to Output 4. Auxiliary Analog Output Left 2. Auxiliary Analog Output Right 2. Test Pin. This pin should be left unconnected. DAC Filter Decoupling Node. Decouple this pin to AGND (Pin 69). Analog Power Supply Pin for the DAC. Connect this pin to 3.3 V and decouple to AGND (Pin 69). DAC Ground. Connect this pin to the analog ground plane. Analog Power Supply Pin for the DAC. Connect this pin to 3.3 V and decouple to AGND (Pin 70). Left Analog Input 1 to Input 4. The analog inputs are current inputs typically driven via a 20 k resistor for 2 V rms input, as shown in Figure 17. Right Analog Input 1 to Input 4. The analog inputs are current inputs typically driven via a 20 k resistor for 2 V rms input, as shown in Figure 17. DAC External Bias Resistor. This is an external bias pin for the DAC circuitry. Connect a 20 k resistor between this pin and AGND.
36 37, 38, 42, 43 39, 44, 45 46 49 50 51 52 53 54 55 56 57 58 to 61 62 63 64 67 68 69, 70 71 72, 74, 76, 78 73, 75, 77, 79 80
LRCLK1 SDO [0:3] NC RESET AVDD2 PLL_LF AGND AGND HPOUTL HPOUTR AVDD3 AUXL1 AUXR1 VOUT [1:4] AUXL2 AUXR2 TEST2 FILTD AVDD4 AGND AVDD5 AINL [1:4] AINR [1:4] IDAC
I/O 0
O O
O O O O O
I I
Rev. 0 | Page 10 of 36
ADAV400 TYPICAL PERFORMANCE CHARACTERISTICS
0
0 -50
MAGNITUDE (dB)
MAGNITUDE (dB)
-50
-100
-150
-100
-200
-250
05811-009 05811-006
-150
0
192
384 FREQUENCY (kHz)
576
768
-300
0
128 256 FREQUENCY (kHz)
384
Figure 6. DAC Composite Filter Response (48 kHz)
Figure 9. ADC Composite Filter Response (48 kHz)
0
0
-50
MAGNITUDE (dB)
MAGNITUDE (dB)
-50
-100
-150
-100
-200
-150
0
24
48 FREQUENCY (kHz)
72
96
-300
0
24
48 FREQUENCY (kHz)
72
96
Figure 7. DAC Pass-Band Filter Response (48 kHz)
0.06 0.006
Figure 10. ADC Pass-Band Filter Response (48 kHz)
0.04
0.004
MAGNITUDE (dB)
0
MAGNITUDE (dB)
0.02
0.002
0
-0.02
-0.002
-0.04
05811-008
-0.004
05811-011
-0.06
0
8
16 FREQUENCY (kHz)
24
-0.006
0
8
16 FREQUENCY (kHz)
24
Figure 8. DAC Pass-Band Ripple (48 kHz)
Figure 11. ADC Pass-Band Ripple (48 kHz)
Rev. 0 | Page 11 of 36
05811-010
05811-007
-250
ADAV400
0 -20 -40
MAGNITUDE (dB) MAGNITUDE (dB)
0
DNR = 95dB (A-WEIGHTED)
-20 -40 -60 -80 -100 -120
05811-012
THD + N = -93dB VIN = -3dBFS
-60 -80 -100 -120 -140 -160
0
4000
8000 12000 FREQUENCY (Hz)
16000
20000
-160
0
4000
8000 12000 FREQUENCY (Hz)
16000
20000
Figure 12. DAC Dynamic Range
0 -20 -40
MAGNITUDE (dB)
Figure 15. ADC Total Harmonic Distortion + Noise
0
THD + N = -94dB VIN = -3dBFS
-5
MAGNITUDE (dB)
-60 -80 -100 -120
05811-013
-10
-15
05811-037
-140 -160
0
4000
8000 12000 FREQUENCY (Hz)
16000
20000
-20
0
0.1
0.2 0.3 FS (Normalized)
0.4
0.5
Figure 13. DAC Total Harmonic Distortion + Noise
0 -20 -40
MAGNITUDE (dB)
Figure 16. Sample Rate Converter Transfer Function
DNR = 95dB (A-WEIGHTED)
-60 -80 -100 -120
05811-014
-140 -160
0
4000
8000 12000 FREQUENCY (Hz)
16000
20000
Figure 14. ADC Dynamic Range
Rev. 0 | Page 12 of 36
05811-015
-140
ADAV400 THEORY OF OPERATION
The ADAV400 is an enhanced audio processor containing an Analog Devices SigmaDSP digital processing core. The core can accept up to four digital stereo channels, typically at 48 kHz, or three channels, typically at 48 kHz, and one channel at any sample rate between 5 kHz and 50 kHz. In addition, up to four stereo analog inputs can be used as the source for the DSP core using the stereo ADC and a four-stereo input mux. Outputs from the DSP core are available as four stereo digital outputs and four stereo analog outputs. The core of the ADAV400 is a 28-bit DSP (56-bit with double precision) optimized for audio processing. Signal processing parameters are stored in a 1024-location parameter RAM. The program RAM can be loaded with a custom program after power-up. New values are written to the program and parameter RAM using the I2C control port. The values stored in the parameter RAM control individual signal processing blocks, such as IIR equalization filters, dynamics processors, audio delays, and mixer levels. A safeload feature allows transparent updating of these parameters, eliminating the risk of unwanted pops or clicks on the outputs. The ADAV400 has a sophisticated control port that supports complete read/write capability of all memory locations except the target/slew RAM and data RAM, which are only accessible by the DSP core. The ADAV400 has a very flexible serial data input and output port that allows for glueless interconnection to a variety of ADCs, DACs, general-purpose DSPs, S/PDIF receivers, and sample rate converters. The digital inputs and outputs of the ADAV400 can be configured in I2S, left-justified, right-justified, or TDM serial port-compatible mode. They can support 16, 20, or 24 bits in all modes. The ADAV400 accepts serial audio data in MSB-first and twos complement formats. The digital core of the ADAV400 operates at 1.8 V, and the other circuit blocks operate from a 3.3 V power supply. An onboard regulator allows a single 3.3 V supply for both digital supplies using the configuration shown in Figure 19. The ADAV400 is fabricated on a single monolithic integrated circuit and is housed in an 80-lead LQFP package for operation over the 0C to 70C consumer temperature range.
47F 20k 47F 20k AINLx AINRx
20k
Figure 17. Analog Input Configuration
SAMPLE RATE CONVERTER BLOCK
The ADAV400 contains a stereo SRC that accepts input sample rates in the range of 5 kHz to 50 kHz. Any one of the digital inputs can be selected as the source for the SRC. Note that the SRC has a filter cutoff frequency of 20 kHz for a 48 kHz sample rate. If a different input sample rate is used, the cutoff frequency scales accordingly.
PLL BLOCK
The ADAV400 contains a phase-locked loop (PLL) that generates all of the internal clocks required by the ADAV400. The master clock frequency can be 64 x fS, 128 x fS, 256 x fS, or 512 x fS. The PLL requires some external components to operate correctly, as shown in Figure 18. These components form a loop filter that integrates pulses from a charge pump and produces a voltage to tune the VCO. Internally the PLL can generate clocks up to 200 MHz, so it is recommended that a suitable capacitor is selected.
AVDD2 100nF 1nF 2k PLL BLOCK PLL_LF
Figure 18. PLL Loop Filter Components
A 3.3 V analog supply connected to AVDD2 is required to operate the PLL. Where the supply for AVDD1 is also used for the PLL, additional filtering is recommended to prevent digital noise created by the PLL block being coupled to the analog circuitry powered by the AVDD1 supply.
ANALOG OUTPUTS
The ADAV400 contains four stereo analog outputs typically at 1 V rms. One stereo pair of DACs is connected to integrated headphone amplifiers HPOUTL and HPOUTR, but is also available on the AUXL1 and AUXR1 pins. Note that the outputs of all the DACs are inverted with the exception of the headphone channel. If required, this can be changed using the invert library block of the DSP.
ANALOG INPUTS
The ADAV400 has four stereo analog inputs. An input multiplexer is included that enables any of these four stereo analog inputs to be connected to the ADC. The analog inputs are current input, see Figure 17 for the suggested input configuration when the required input level is 2 V rms.
Rev. 0 | Page 13 of 36
05811-018
05811-016
IDAC
ADAV400
HEADPHONE AMPLIFIER
The ADAV400 has an integrated stereo headphone amplifier capable of driving 32 mW into a 32 load.
VDRIVE ODVDD
VDD + + +
DVDD
The ADAV400 includes an on-chip voltage regulator that enables the chip to be used in systems where a 1.8 V supply is not available. The only external components needed are a PNP transistor (such as FZT953), a single capacitor, and a single resistor. The recommended design for the voltage regulator is shown in Figure 19. Here, VDD is the main system voltage (3.3 V). A voltage of 1.8 V is generated at the transistor's collector and is connected to the DVDD pins. VDRIVE is an output from the internal regulator circuit on the ADAV400 and is connected to the base of the PNP transistor
Figure 19. Voltage Regulator Design
There are two specifications to take into consideration when choosing the regulator's transistor. First, hFE should be at least 100. Second, the collector power dissipation, PC, must be greater than PC = (3.3 V - 1.8 V) x 135 mA = 202.5 mW
Rev. 0 | Page 14 of 36
05811-019
ADAV400
DVDD
VOLTAGE REGULATOR
ADAV400 CONTROL PORT
The ADAV400 control port has full read and write capability to all registers and RAMs with the exception of the data RAM, which is only accessible by the DSP core. Single or burst mode read and writes are supported. A typical word consists of the chip address, the register or RAM subaddress, and the data to be written. The number of bytes per data-word depends on the address of the location being written to or read from. The first byte of a control word (Byte 0) contains the 7-bit chip address plus the R/W bit. The next two bytes (Byte 1 and Byte 2) together form the subaddress of the memory or register location within the ADAV400. All subsequent bytes contain data that can be writes to the control register or updates to the program and parameter memories. Table 16 to Table 25 provide more details on the I2C write and read format. The ADAV400 has several mechanisms for updating signal processing parameters in real time without causing pops or clicks. In cases where large blocks of data need to be transferred, it is recommended to mute the output of the DSP core by setting Bit 9 of the audio core control register to 0, load the new data, and then set Bit 9 back to 1. This is typically done during the booting sequence at startup, or when loading a new program into RAM. In cases where only a few parameters need to be changed--for example, updating a biquad--the new parameters can be loaded without halting the program. To avoid unwanted pops or clicks on the output during the loading sequence, the DSP core uses an internal safeload mechanism that buffers the data and only updates the parameter memory at the end of the sample period and before the start of the next sample period Table 5. I2C Addresses
AD0 0 0 1 1 R/W 0 1 0 1 Slave Address 0x28 0x29 0x2A 0x2B
Addressing
Initially, all devices on the I2C bus are in an idle state, wherein the devices monitor the SDA and SCL lines for a start condition and the proper address. The I2C master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream follows. All devices on the bus respond to the start condition and read the next byte (7-bit address + R/W bit) MSB first. The device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This ninth bit is known as an acknowledge bit. All other devices on the bus revert to an idle condition. The R/W bit determines the direction of the data. A Logic Level 0 on the LSB of the first byte means the master writes information to the peripheral. A Logic Level 1 on the LSB of the first byte means the master reads information from the peripheral. A data transfer takes place until a stop condition is encountered. A stop condition occurs when SDA transitions from low to high while SCL is held high. Figure 20 shows the timing of an I2C write. Burst mode addressing, where the subaddresses are automatically incremented at word boundaries, can be used for writing large amounts of data to contiguous memory locations. This increment happens automatically if a stop condition is not encountered after a single word write. A data transfer is always terminated by a stop condition. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, it causes an immediate jump to the idle condition. During a given SCL high period, the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADAV400 does not issue an acknowledge and reverts to an idle state. If the user exceeds the highest subaddress while in autoincrement mode, one of two actions is taken. In read mode, the ADAV400 outputs the highest subaddress register contents until the master device issues a no acknowledge, indicating the end of a read. A no acknowledge condition is where the SDA line is not pulled low on the ninth clock pulse on SCL. If the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADAV400, and the part returns to the idle condition.
I2C PORT
The ADAV400 supports a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. Two pins, serial data (SDA) and serial clock (SCL), carry information between the ADAV400 and the system I2C master controller. The ADAV400 is always a slave on the I2C bus, which means that it never initiates a data transfer. Each slave device is recognized by a unique address. The ADAV400 has four possible slave addresses, two for writing operations and two for reading operations. These are unique addresses for the device and are illustrated in Table 5. The LSB of the byte sets either a read or a write operation; Logic Level 1 corresponds to a read operation, and Logic Level 0 corresponds to a write operation. The seventh bit of the address is set by tying the AD0 pin of the ADAV400 to Logic Level 0 or Logic Level 1.
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ADAV400
I2C Read and Write Operations
Table 6 shows the timing of a single word write operation. Every ninth clock, the ADAV400 issues an acknowledge by pulling SDA low. Table 7 shows the timing of a burst mode write sequence. This table shows an example where the target destination registers are two bytes. The ADAV400 auto-increments its subaddress register counter every two bytes until a stop condition occurs. The timing of a single word read operation is shown in Table 8. Note that the first R/W bit is still a 0, indicating a write operation. This is because the subaddress must be written to set up the internal address. After the ADAV400 acknowledges the receipt of the subaddress, the master must issue a repeated start command followed by the chip address byte with the R/W set to 1 (read). The ADAV400 responds with the read result on SDA. The master then responds every ninth clock with an acknowledge pulse to the ADAV400. Table 9 shows the timing of a burst mode read sequence. This table shows an example where the target read registers are two bytes. The ADAV400 increments its subaddress register every two bytes because the requested subaddress corresponds to a register or memory area with word lengths of two bytes. Other address ranges may have a variety of word lengths ranging from one to six bytes; the ADAV400 always decodes the subaddress and sets the auto-increment circuit so that the address increments after the appropriate number of bytes.
Key for Table 6 to Table 9: S = start bit P = stop bit AM = acknowledge by master AS = acknowledge by slave Table 6. Single Word I2C Write
S Chip address, R/W = 0 AS Subaddress high AS Subaddress low AS Data Byte 1 AS Data Byte 2 ... AS Data Byte N P
Table 7. Burst Mode I2C Write
S Chip address, R/W = 0 AS Subaddress high AS Subaddress low AS Data-Word 1 Byte 1 AS Data-Word 1 Byte 2 AS Data-Word 2 Byte 1 AS Data-Word 2 Byte 2 AS ... P
Table 8. Single Word I2C Read
S Chip address, R/W = 0 AS Subaddress high AS Subaddress low AS S Chip address, R/W = 1 AS Data Byte 1 AM Data Byte 2 ... AM Data Byte N P
Table 9. Burst Mode I2C Read
S Chip address, R/W = 0 AS Subaddress high AS Subaddress low AS S Chip address, R/W = 1 AS Data-Word 1 Byte 1 AM Data-Word 1 Byte 2 AM ... P
Rev. 0 | Page 16 of 36
ADAV400
SCL
SDA START BY MASTER
0
0
1
0
1
0
ADR SEL
R/W ACK. BY ADAV400 ACK. BY ADAV400 FRAME 2 SUBADDRESS BYTE 1
FRAME 1 CHIP ADDRESS BYTE
SCL (CONTINUED) SDA (CONTINUED) FRAME 2 SUBADDRESS BYTE 2
FRAME 3 DATA BYTE 1
Figure 20. I2C Write Format
SCL
SDA START BY MASTER
0
0
1
0
1
0
ADR SEL
R/W ACK. BY ADAV400 ACK. BY ADAV400 FRAME 2 SUBADDRESS BYTE 1
FRAME 1 CHIP ADDRESS BYTE SCL (CONTINUED) SDA (CONTINUED) ACK. BY REPEATED ADAV400 START BY MASTER
0
0
1
0
1
0
ADR SEL
R/W ACK. BY ADAV400
FRAME 3 SUBADDRESS BYTE 2 SCL (CONTINUED) SDA (CONTINUED)
FRAME 4 CHIP ADDRESS BYTE
FRAME 5 READ DATA BYTE 1
FRAME 6 READ DATA BYTE 1
Figure 21. I2C Read Format
Rev. 0 | Page 17 of 36
05811-022
ACK. BY MASTER
ACK. BY MASTER
STOP BY MASTER
05811-021
ACK. BY ADAV400
ACK. BY ADAV400
STOP BY MASTER
ADAV400 SIGNAL PROCESSING
The ADAV400 is designed to provide all the signal processing functions commonly used in stereo or multichannel playback systems. The signal processing flow is created using a graphical development tool supplied by Analog Devices, which allows fast development of even complex audio flows and real-time control of all signal-processing functions. The input and output word lengths are 24 bits. Four extra headroom bits are used in the processor to allow internal gains of up to 24 dB without clipping. The signal processing blocks can be arranged in a custom program that is loaded to the RAM of the ADAV400. The available signal processing blocks are outlined in the Numeric Formats and Programming sections.
4-BIT SIGN EXTENSION SIGNAL PROCESSING (5.23 FORMAT) 1.23 5.23 5.23 DIGITAL CLIPPER 1.23
05811-020
DATA IN
SERIAL PORT
Figure 22. Numeric Precision and Clipping Structure
PROGRAMMING
On power-up, the default program of the ADAV400 passes the unprocessed input signals to the outputs, but the outputs are muted by default. There are 2560 instruction cycles per audio sample. This DSP runs in a stream-oriented manner, meaning all 2560 instructions are executed each sample period. The ADAV400 can also be set up to accept double- or quad-speed inputs by reducing the number of instructions per sample. This is set in the audio core control register. The part is easily programmed using graphical tools provided by Analog Devices. No knowledge of DSP assembly code is required to program the ADAV400. Simply connect graphical blocks, such as biquad filters, dynamics processors, mixers, and delays, in a signal flow schematic. The schematic is then compiled, and the program and parameter files are loaded into the program RAM of the ADAV400 through the control port. Signal processing blocks available in the provided libraries include * * * * * * * * * * * * Single- and double-precision biquad filters Monochannel and multichannel dynamics processors Mixers and splitters Tone and noise generators First-order filters Fixed and variable gain RMS look-up tables Loudness Delay Stereo enhancement (Phat StereoTM) Dynamic bass boost Interpolators and decimators
NUMERIC FORMATS
It is common in DSP systems to use a standardized method of specifying numeric formats. Fractional number systems are specified by an A.B format, where A is the number of bits to the left of the decimal point and B is the number of bits to the right of the decimal point. The ADAV400 uses the same numeric format for both the coefficient values (stored in the parameter RAM) and the signal data values.
Numeric Format: 5.23
Range: -16.0 to (+16.0 - 1 LSB) Examples: 1000 0000 0000 0000 0000 0000 0000 = -16.0 1110 0000 0000 0000 0000 0000 0000 = -4.0 1111 1000 0000 0000 0000 0000 0000 = -1.0 1111 1110 0000 0000 0000 0000 0000 = -0.25 1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0.0) 0000 0000 0000 0000 0000 0000 0000 = 0.0 0000 0010 0000 0000 0000 0000 0000 = +0.25 0000 1000 0000 0000 0000 0000 0000 = +1.0 0010 0000 0000 0000 0000 0000 0000 = +4.0 0111 1111 1111 1111 1111 1111 1111 = (+16.0 - 1 LSB) The serial port accepts up to 24 bits on the input and is signextended to the full 28 bits of the core. This allows internal gains of up to 24 dB without encountering internal clipping. A digital clipper circuit is used between the output of the DSP core and the serial output ports (see Figure 22). This clips the top four bits of the signal to produce a 24-bit output with a range of +1.0 (-1 LSB) to -1.0.
Additional blocks are always in development. Analog Devices also provides proprietary and third-party algorithms for applications such as matrix decoding, bass enhancement, and surround virtualizers. Contact Analog Devices for information about licensing these algorithms.
Rev. 0 | Page 18 of 36
ADAV400 RAMS AND REGISTERS
Table 10. Control Port Addresses
I2C Subaddress 0 to 1023 (0x0000 to 0x03FF) 1024 to 3584 (0x0400 to 0x0E00) 4096 to 4159 (0x1000 to 0x103F) 4160 to 4164 (0x1040 to 0x1044) 4165 to 4169 (0x1045 to 0x1049) 4170 to 4175 (0x104A to 0x104F) 4176 to 4177 (0x1050 to 0x1051) 4178 (0x1052) 4179 (0x1053) 4180 (0x1054) 4181 (0x1055) 4182 (0x1056) 4183 (0x1057) 4184 (0x1058) 4185 (0x1059) 4186 (0x105A) 4365 (0x110D) Register Name Parameter RAM Program RAM Target/slew RAM Parameter RAM Data Safeload Register [0:4] Parameter RAM Indirect Address Safeload Register [0:4] Data Capture Register [0:5] (control port readback) Data capture registers (digital output) Audio core control register RAM modulo control register Serial output control register Serial input control register SRC serial port control register ADC input mux control register Power control register User Control 1 register User Control 2 register DAC amplifier register Read/Write Word Length Write: 4 bytes; read: 4 bytes Write: 6 bytes; read: 6 bytes Write: 5 bytes; read: N/A Write: 5 bytes; read: N/A Write: 2 bytes; read: N/A Write: 2 bytes; read: 3 bytes Write: 2 bytes; read: N/A Write: 2 bytes; read: 2 bytes Write: 1 byte; read: 1 byte Write: 2 bytes; read: 2 bytes Write: 1 byte; read: 1 byte Write: 1 byte; read: 1 byte Write: 2 bytes; read: 2 bytes Write: 2 bytes; read: 2 bytes Write: 2 bytes; read: 2 bytes Write: 2 bytes; read: 2 bytes Write: 2 bytes; read: 2 bytes
Table 11. RAM Read/Write Modes
Memory Parameter RAM Program RAM Target/Slew RAM
1
Size 1024 x 28 2560 x 42 64 x 34
Subaddress Range 0 to 1023 (0x0000 to 0x03FF) 1024 to 3584 (0x0400 to 0x0E00) 4096 to 4159 (0x1000 to 0x1044)
Read Yes Yes No
Write Yes Yes Yes
Burst Mode Available Yes Yes No
Write Modes Direct write, 1 safeload write Direct write1 Safeload write
To avoid clicks or pops, mute the DSP core first.
CONTROL PORT ADDRESSING
Table 10 shows the addressing of the RAM and register spaces on the ADAV400. The address space encompasses a set of registers and three RAMs: parameter, program, and target\slew. Table 11 lists the sizes and available writing modes of the parameter, program, and target/slew RAMs.
Options for Parameter Updates
The parameter RAM can be written to and read from using one of the two following methods: * Direct Read/Write. This method allows direct access to the program and parameter RAMs. This mode of operation is normally used during a complete new load of the RAMs using burst mode addressing. To avoid clicks or pops in the outputs, it is recommended to set the clear registers bit in the audio core control register to 0. Safeload Write. Up to five safeload registers can be loaded with parameter RAM address data. The data is transferred to the requested address when the RAM is idle. It is recommended to use this method for dynamic updates during run time. For example, a complete update of one biquad section can occur in one audio frame. This method is not available for writing to the program RAM or control registers. The following sections discuss these two options in more detail.
PARAMETER RAM CONTENTS
The parameter RAM is 28 bits wide and occupies Address 0 to Address 1023. The parameter RAM is initialized to all 0s on power-up. The data format of the parameter RAM is twos complement 5.23. This means that the coefficients can range from +16.0 (-1 LSB) to -16.0, with 1.0 represented by the binary word 0000 1000 0000 0000 0000 0000 0000.
*
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ADAV400
RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURES
When writing large amounts of data to the program or parameter RAM in direct write mode, disable the processor core to prevent pops or clicks at the audio output. The ADAV400 contains several mechanisms for disabling the core. If the loaded program does not use the target/slew RAM as the main system volume control (for example, the default power-up program), 1. Assert Bit 9 (low to assert--default setting) and Bit 6 (high to assert) of the audio core control register. This clears the accumulators, the serial output registers, and the serial input registers. Fill the program RAM using burst mode writes. Fill the parameter RAM using burst mode writes. Assert Bit 7 of the audio core control register to initiate a data memory clear sequence. Wait at least 100 s for this sequence to complete. This bit is automatically cleared after the operation is complete. Deassert Bit 9 and Bit 6 of the audio core control register to allow the core to begin normal operation When a program is loaded into the program RAM using one or more locations in the slew RAM to access internal coefficient data, the target/slew RAM is used by the DSP. Typically, these coefficients are used for volume controls or smooth cross-fading effects, but they can also be used to update any value in the parameter RAM. Each of the 64 locations in the slew RAM is linked to corresponding location in the target RAM. When a new value is written to the target RAM using the control port, the corresponding slew RAM location begins to ramp toward the target. The value is updated once per audio frame (LRCLK period). The target RAM is 34 bits wide. The lower 28 bits contain the target data in 5.23 format for the linear and exponential (constant dB and RC) ramp types. For constant time ramping, the lower 28 bits contain 16 bits in 2.14 format and 12 bits to set the current step. The upper six bits are used to determine the type and speed of the ramp envelope in all modes. The format of the data write for linear and exponential formats is shown in Table 12. Table 13 shows the data write format for the constant time ramping. In normal operation, write data to the target/slew RAM using the safeload registers as described in the Safeload Registers section. A mute slew RAM bit is included in the audio core control register to simultaneously set all the slew RAM target values to 0. This is useful for implementing a global multichannel mute. When this bit is deasserted, all slew RAM values return to their original premuted states. Table 12. Linear, Constant dB, and RC Ramp Data Write
Byte 0 000000, curve_type [1:0] Byte 1 time_const [3:0], data [27:24] Bytes [2:4] data [23:0]
2. 3. 4.
5.
If the loaded program does use the target/slew RAM as the main system volume control, 1. Assert Bit 12 of the audio core control register. This begins a volume ramp-down, with a time constant determined by the upper bits of the target RAM. Wait for this ramp-down to complete (the user can poll Bit 13 of the audio core control register, or simply wait for a given amount of time). Assert Bit 9 (low to assert) and Bit 6 (high to assert) of the audio core control register. This clears the accumulators, the serial output registers, and the serial input registers. Fill the program RAM using burst mode writes. Fill the parameter RAM using burst mode writes. Assert Bit 7 of the audio core control register to initiate a data memory clear sequence. Wait at least 100 s for this sequence to complete. This bit is automatically cleared after the operation is complete. Deassert Bit 9 and Bit 6 of the audio core control register. If the newly loaded program also uses the target/slew RAM, deassert Bit 12 of the audio core control register to begin a volume ramp-up procedure.
Table 13. Constant Time Ramp Data Write
Byte 0 000000, curve_type [1:0] Byte 1 update_step [0], #_of_steps [2:0], data [15:12] Bytes [2:4] data [11:0], reserved [11:0]
2.
3. 4. 5.
There are four types of ramping curve: * * Linear. The value slews to the target value using a fixed step size. Constant dB. The value slews to the target value using the current value to calculate the step size. The resulting curve has a constant rise and decay when measured in decibels. RC. The value slews to the target value using the difference between the target and current value to calculate the step size, resulting in a simple RC response. Constant Time. The value slews to the target value in a fixed number of steps in a linear fashion. The control port mute has no effect on this type of ramping curve.
6. 7.
*
TARGET/SLEW RAM
The target/slew RAM is a bank of 64 RAM locations, each of which can be set to autoramp from one value to a desired final value in one of four modes. *
Rev. 0 | Page 20 of 36
ADAV400
Table 14. Target/Slew RAM Ramp Type Settings
Settings 00 01 10 11 Ramp Type Linear Constant dB RC Constant time
Linear Update
A linear update is the addition or subtraction of a constant value, referred to as a step. The equation to describe this step size is
Step =
10
2x (tCONST - 5 )
213
20
The following sections detail how the control port writes to the target/slew RAM to control the time constant and ramp type parameters.
Ramp Types [1:3]--Linear, Constant dB, RC (34-Bit Write)
The target word for the first three ramp types is broken into three parts. The 34-bit command is written with six leading 0s to extend the data write to five bytes. The parts of the target RAM write are * * Ramp type (2 bits). Time constant (4 bits). 0000 = fastest 1111 = slowest Data (28 bits): 5.23 format.
The result of the equation is normalized to a 5.23 data format. This produces a time constant range from 6.75 ms to 213.4 ms. (-60 dB relative to 0 dB full scale). An example of this kind of update is shown in Figure 23 and Figure 24. All slew RAM figure examples, except the half-scale constant time ramp plot (Figure 29), show an increasing or decreasing ramp between -80 dB and 0 dB (full scale). All figures except the constant time plots (Figure 28 and Figure 29) use a time constant of 0x7 (0x0 being the fastest and 0xF being the slowest).
1.0 0.8 0.6
OUTPUT LEVEL (V)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30
05811-023
*
Ramp Type 4--Constant Time (34-Bit Write)
The target word for the constant time ramp type is written in five parts, with the 34-bit command written with six leading 0s to extend the data write to five bytes. The parts of the constant time target RAM write are * * Ramp type (2 bits). Update step (1 bit). Set to 1 when a new target is loaded to trigger a step value update. The value is automatically reset after the step value is updated. Number of steps (3 bits). The number of steps needed to slew to the target value is set by these three bits, with the number of steps equal to 23-bit setting + 6. 000 = 64 001 = 128 010 = 256 011 = 512 100 = 1024 101 = 2048 110 = 4096 111 = 8196 Data (16 bits): 2.14 format. Reserved (12 bits). When writing to the RAM, set all of these bits to 0.
35
Figure 23. Slew RAM--Linear Update Increasing Ramp
1.0 0.8 0.6
OUTPUT LEVEL (V)
*
0.4 0.2 0 -0.2 -0.4 -0.6
05811-024
-0.8 -1.0
* *
0
5
10
20 15 TIME (ms)
25
30
35
Figure 24. Slew RAM--Linear Update Decreasing Ramp
Target/Slew RAM Initialization
On reset, the target/slew RAM initializes to preset values. The target RAM initializes to a linear ramp type with a time constant of 5 and the data set to 1.0. The slew RAM initializes to a value of 1.0. These defaults result in a full-scale (1.0 to 0.0) ramp time of 21.3 ms.
Rev. 0 | Page 21 of 36
ADAV400
Constant dB and RC Updates (Exponential)
An exponential update is accomplished by shifts and additions with a range from 6.1 ms to 1.27 sec (-60 dB relative to 0 dB full scale). When the ramp type is set to 01 (constant dB), each step size is set to the current value in the slew data. When the ramp type bits are set to 10 (RC), the step size is equal to the difference between the values in the target RAM and slew RAM (see Figure 25, Figure 26, and Figure 27).
1.0 0.8 0.6
OUTPUT LEVEL (V)
Constant Time Update
A constant time update is calculated by adding a step value that is determined after each target is loaded. The equation for this step size is Step = (Target Data - Slew Data)/(Number of Steps) Figure 28 shows a plot of the target/slew RAM operating in constant time mode. For this example, 128 steps are used to reach the target value. This type of ramping takes a fixed amount of time for a given number of steps, regardless of the difference in the initial state and the target value. Figure 29 shows a plot of a constant time ramp from -80 dB to -6 dB (half scale) using 128 steps; thus, the ramp takes the same amount of time as the previous ramp from -80 dB to 0 dB. A constant time decreasing ramp plot is shown in Figure 30.
1.0 0.8 0.6
05811-025
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30
OUTPUT LEVEL (V)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30
05811-028
35
Figure 25. Slew RAM--Constant dB Update Increasing Ramp
1.0 0.8 0.6
OUTPUT LEVEL (V)
0.4 0.2 0 -0.2 -0.4 -0.6
05811-026
35
Figure 28. Slew RAM--Constant Time Update Increasing Ramp, Full Scale
1.0 0.8 0.6
OUTPUT LEVEL (V)
-0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30
05811-029
35
Figure 26. Slew RAM--RC Update Increasing Ramp
1.0 0.8 0.6
OUTPUT LEVEL (V)
0.4 0.2 0 -0.2 -0.4 -0.6
05811-027
35
Figure 29. Slew RAM--Constant Time Update Increasing Ramp, Half Scale
-0.8 -1.0
0
5
10
15 20 TIME (ms)
25
30
35
Figure 27. Slew RAM--Constant dB and RC Updates Decreasing Ramp, Full Scale
Rev. 0 | Page 22 of 36
ADAV400
1.0 0.8 0.6
OUTPUT LEVEL (V)
0.4 0.2 0 -0.2 -0.4 -0.6
05811-030
The ADAV400 data capture feature allows the data at any node in the signal processing flow to be sent to one of six controlport-readable registers or to a serial output pin. Use this feature to monitor and display information about internal signal levels or compressor/limiter activity. The ADAV400 contains six independent data capture registers that can be read via the I2C control port and can be used for monitoring static signals. In addition, two I2S digital output capture registers are available for monitoring dynamic signals. For each of the data capture registers, a capture count and a register select must be set. The capture count is a number between 0 and 2559 that corresponds to the program step number where the capture will occur (see Table 15). Table 15. Data Capture Control Registers
Register Bits 13:2 1:0 Function 12-bit program counter address Register select 00 = Mult_X_input 01 = Mult_Y_input 10 = MAC_output 11 = Accum_fback
-0.8 -1.0
0
5
10
15 20 TIME (ms)
25
30
35
Figure 30. Slew RAM--Constant Time Update Decreasing Ramp, Full Scale
SAFELOAD REGISTERS
Many applications require real-time control of signal processing parameters, such as filter coefficients, mixer gains, multichannel virtualizing parameters, or dynamics processing curves. For example, if we consider a biquad to prevent instability from occurring, all five parameters of a biquad filter must be updated at the same time. Otherwise, the filter may execute with a mix of old and new coefficients for one or two audio frames. To eliminate this problem, the ADAV400 uses the safeload registers; there are five registers for the 28-bit parameter data and five for the parameter addresses. These addresses will indirectly address either the parameter RAM or the target/slew RAM. Once these registers are loaded, the appropriate initiate safe transfer bit (there are separate bits for parameter and target/slew loads) in the audio core control register should be set. The last five instructions of the program RAM are used for the safeload process, so the program length should be limited to 2555 cycles (2560 - 5). It is guaranteed that the safeload occurs within one LRCLK period (21 s at fS = 48 kHz) of the initiate safe transfer bit being set. Safeload only updates those safeload registers that have been loaded with new data since the last safeload operation. For example, if only two parameters or target RAM locations are to be updated, it is only necessary to load two of the safeload registers; the other safeload registers are ignored because they contain old data.
The register select field selects which one of four registers within the DSP core will be transferred to the data capture register when the program counter equals the capture count. The capture count and register select bits are set by writing to one of the eight data capture registers at the following register addresses: 4170: Control Port Data Capture Setup Register 0 4171: Control Port Data Capture Setup Register 1 4172: Control Port Data Capture Setup Register 2 4173: Control Port Data Capture Setup Register 3 4174: Control Port Data Capture Setup Register 4 4175: Control Port Data Capture Setup Register 5 4176: Digital Out Data Capture Setup Register 0 4177: Digital Out Data Capture Setup Register 1 The captured data is in 5.19 twos complement data format for all eight register select fields. The four LSBs are truncated from the internal 5.23 data-word. The formats for writing and reading to the data capture registers are listed in Table 22 and Table 23.
DATA CAPTURE REGISTERS
Data capture registers are used for debugging user-programmed blocks and are not required when using pre-existing library blocks.
Rev. 0 | Page 23 of 36
ADAV400
CONTROL PORT READ/WRITE DATA FORMATS
The read/write formats of the control port are designed to be byte-oriented. To conform to this byte-oriented format, 0s are appended to the data fields before the MSB to extend the dataword to the next multiple of eight bits. For example, for parameter RAM a 28-bit word is appended with four leading 0s, making the transfer 4 bytes; for program RAM a 42-bit word is appended with six leading 0s, making the transfer 6 bytes. The data fields are appended to a 3-byte field consisting of a 7-bit chip address, a read/write bit, and an 11-bit RAM/register address for full I2C transfer. Burst mode is used to fill contiguous register or RAM locations. A burst mode write is done by writing the address and data of the first RAM/register location to be written followed by the next data-word, and so on. The ADAV400 control port autoincrements the internal address counter depending on the location being written to or read from, even across the boundaries of the different RAMs and registers locations.
Table 16. Parameter RAM Read/Write Format (Single Address)
Byte 0 chip_adr [6:0], R/W Byte 1 000, param_adr [12:8] Byte 2 param_adr [7:0] Byte 3 0000, param [27:24] Bytes 4 to 6 param [23:0]
Table 17. Parameter RAM Block Read/Write Format (Burst Mode)
Byte 0 chip_adr [6:0], R/W Byte 1 000, param_adr [12:8] Byte 2 param_adr [7:0] Byte 3 0000, param [27:24] Bytes 4 to 6 param [23:0] Bytes 7 to 10 0000 param [27:0] Second parameter (param_adr + 1) Bytes 11 to 14 0000 param [27:0] Third parameter (param_adr + 2)
First parameter (param_adr)
Table 18. Program RAM Read/Write Format (Single Address)
Byte 0 chip_adr [6:0], R/W Byte 1 000, prog_adr [12:8] Byte 2 prog_adr [7:0] Bytes 3 to 8 prog [42:0]
Table 19. Program RAM Block Read/Write Format (Burst Mode)
Byte 0 chip_adr [6:0], R/W Byte 1 000, prog_adr [12:8] Byte 2 prog_adr [7:0] Bytes 3 to 8 prog [39:0] Bytes 9 to 14 Second program word (prog_adr + 1) Bytes 15 to 20 Third program word (prog_adr + 2)
First program word (prog_adr)
Table 20. Control Register Read/Write Format (16-bit register)
Byte 0 chip_adr [6:0], R/W Byte1 000, reg_adr [12:8] Byte 2 reg_adr [7:0] Byte 3 data [15:8] Byte 4 data [7:0]
Table 21. Control Register Read/Write Format (8-bit register)
Byte 0 chip_adr [6:0], R/W Byte1 000, reg_adr [12:8] Byte 2 reg_adr [7:0] Byte 3 data [7:0]
Table 22. Data Capture Register Write Format
Byte 0 chip_adr [6:0], R/W Byte 1 000, data_capture_adr [12:8] Byte 2 data_capture_adr [7:0] Byte 3 000, progCount [10:6] Byte 4 progCount [5:0], regSel [1:0]
Table 23. Data Capture (Control Port Readback) Register Read Format
Byte 0 chip_adr [6:0], R/W Byte 1 000, data_capture_adr [12:8] Byte 2 data_capture_adr [7:0] Bytes 3 to 5 data [23:0]
Rev. 0 | Page 24 of 36
ADAV400
Table 24. Safeload Register Data Write Format
Byte 0 chip_adr [6:0], R/W Byte 1 000, safeload_adr [12:8] Byte 2 safeload_adr [7:0] Byte 3 000000, data [33:32] Bytes 4 to 7 data [31:0]
Table 25. Safeload Register Address Write Format
Byte 0 chip_adr [6:0], R/W Byte 1 000, safeload_adr [12:8] Byte 2 safeload_adr [7:0] Byte 3 0000, param_adr [11:8] Byte 4 param_adr [7:0]
Rev. 0 | Page 25 of 36
ADAV400 SERIAL DATA INPUT/OUTPUT PORTS
The flexible serial data input/output ports of the ADAV400 can be set to accept or transmit data in 2-channel format or in an 8- or 16-channel TDM stream. Data is processed in twos complement, MSB-first format. The left channel data field always precedes the right channel data field in the 2-channel streams. In the TDM modes, Slot 0 to Slot 3 (8-channel TDM) or Slot 0 to Slot 7 (16-channel TDM) fall in the first half of the audio frame, and Slot 4 to Slot 7 (or Slot 8 to Slot 15 in 16-channel TDM) are in the second half of the frame. The serial modes are set in the serial input and output control registers. The input and output control register define the operation of the serial ports. Because BCLK1 and LRCLK1 are used for both input and output serial port timing, some care must be taken when individually programming serial modes. For example, Table 26. Serial Output Port Master/Slave Mode Capabilities
fS 48 kHz 96 kHz 192 kHz 2-Channel Modes (I2S, Left-Justified, Right-Justified) Master and slave Master and slave Master and slave 8-Channel TDM Master and slave Master and slave Slave only 16-Channel TDM Slave only Slave only Slave only
programming the input serial port to TDM and the output port to left-justified is not a valid state. In TDM mode, there are some restrictions to ADAV400 operation, which are outlined in Table 26. There are two modes of operation. In both 8-channel and 16-channel TDM modes, SDIN0 is the input for the TDM stream and SDO0 is the output. Figure 34 shows the ADAV400 operating in TDM mode. Refer to the Serial Data Input/Output Ports section for a more complete description of the modes of operation. Note that in 16-channel TDM mode, the ADC and DACs are no longer used because all 16 input and output channels have been redirected to the serial input and output ports.
Table 27. Data Format Configurations
Format I2S (Figure 31) Left-Justified (Figure 32) Right-Justified (Figure 33) TDM with Clock (Figure 34) TDM with Pulse (Figure 35) LRCLK Polarity Frame begins on falling edge Frame begins on rising edge Frame begins on rising edge Frame begins on falling edge Frame begins on rising edge LRCLK Type Clock Clock Clock Clock Pulse BCLK Polarity Data changes on falling edge Data changes on falling edge Data changes on falling edge Data changes on falling edge Data changes on falling edge MSB Position Delayed from LRCLK edge by one BCLK Aligned with LRCLK edge Delayed from LRCLK edge by 8, 12, or 16 BCLKs Delayed from start of word clock by one BCLK Delayed from start of word clock by one BCLK
Rev. 0 | Page 26 of 36
ADAV400
LRCLK BCLK
05811-031
05811-035
05811-033
LEFT CHANNEL
RIGHT CHANNEL
SDATA
MSB
LSB 1 /FS
MSB
LSB
Figure 31. I2S Mode--16 to 24 Bits per Channel
LRCLK BCLK SDATA MSB
LEFT CHANNEL LSB MSB 1 /FS
RIGHT CHANNEL
05811-032
LSB
Figure 32. Left-Justified Mode--16 to 24 Bits per Channel
LRCLK BCLK SDATA MSB
LEFT CHANNEL LSB 1 /FS
RIGHT CHANNEL
MSB
LSB
Figure 33. Right-Justified Mode--16 to 24 Bits per Channel
LRCLK 256 BCLKs BCLK 32 BCLKs SLOT 0 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7
DATA
LRCLK
05811-034
BCLK MSB MSB-1 MSB-2 DATA
Figure 34. 8-Channel TDM Mode with Clock
LRCLK
BCLK
MSB TDM SDATA
CH 0
MSB TDM
8TH CH
SLOT 0 SDIN0L 32 BCLKs
SLOT 1 SDIN0R
SLOT 2 SDIN1L
SLOT 3 SDIN1R
SLOT 4 SDIN2L
SLOT 5 SDIN2R
SLOT 6 SDIN3L
SLOT 7 SDIN3R
Figure 35. TDM Mode with Pulse Word Clock
Rev. 0 | Page 27 of 36
ADAV400 CONTROL REGISTERS
Table 28. Audio Register Map
Register Address (Hex) 0x1052 0x1053 0x1054 0x1055 0x1056 0x1057 0x1058 0x1059 0x105A 0x110D 0x1113 Register Name Audio core control register (see Table 29) RAM modulo control register (see Table 30) Serial output control register (see Table 31) Serial input control register (see Table 32) SRC serial port control register (see Table 33) ADC input mux control register (see Table 34) Power control register (see Table 35) User Control Register 1 (see Table 37) User Control Register 2 (see Table 36) DAC amplifier register (see Table 38) Headphone amplifier register (see Table 39) Register Width (Bits) 16 8 16 8 8 16 16 16 16 16 16
Table 29. Audio Core Control Register Register Address 0x1052 Default Readback = 0x4000
Register Bits 15 141 Function Reserved (set to 0) Enable SDO2 and SDO3 0 = enabled 1 = disabled Indicates when slew RAM is muted (read only) Equivalent to writing 0s to the target RAM 0 = normal operation 1 = RAM zeroed Reserved (set to 0) Reserved (set to 0) Clears internal processor registers (active low) 0 = registers cleared 1 = normal operation Forces multiplier input to 0 0 = normal operation 1 = forced to 0 Initializes data RAM to zero 0 = normal operation 1 = enabled Register Bits 6 Function Mutes serial input ports 0 = normal operation 1 = muted Initiates safeload-to-target/slew RAM 0 = off 1 = on Initiates safeload-to-parameter RAM 0 = off 1 = on Reserved (set to 0) Programs length 00 = 2560 (48 kHz) 01 = 1280 (96 kHz digital IO only) 10 = 640 (192 kHz digital IO only) 11 = reserved
5
13 12
4
11 10 9
3:2 1:0
8
1
The polarity of this bit is inverted when read.
7
Rev. 0 | Page 28 of 36
ADAV400
Table 30. RAM Modulo Control Register (8 Bits)
Register Address 0x1053 Default = 0x28 Register Bits Function 7:6 Reserved (set to 0) 5:0 RAM modulo size (1 LSB = 512 locations)
Table 32. Serial Input Control Register (8 Bits)
Register Address 0x1055 Default = 0x00 Register Bits Function 7:6 Reserved (set to 0) 5 TDM input mode 0 = 8-channel TDM 1 = 16-channel TDM 4 LRCLK polarity 0 = left low, right high 1 = left high, right low 3 BCLK polarity 0 = data changes on falling edge 1 = data changes on rising edge 2:0 Serial input mode 000 = I2S 001 = left-justified 010 = 8-channel TDM 011 = right-justified, 24 bits 100 = right-justified, 20 bits 101 = right-justified, 18 bits 110 = right-justified, 16 bits All others are reserved
Table 31. Serial Output Control Register
Register Address 0x1054 Default = 0x0000 Register Bits Function 15 Dither enable 0 = disabled 1 = enabled 14 TDM output mode 0 = 8-channel TDM 1 = 16-channel TDM 13 LRCLK polarity 0 = left low, right high 1 = left high, right low 12 BCLK polarity 0 = data changes on falling edge 1 = data changes on rising edge 11 Master/slave mode select 0 = slave 1 = master 10:9 BCLK frequency (master mode) 00 = 3.072 MHz (48 kHz) 01 = 6.144 MHz (96 kHz digital IO only) 10 = 12.288 MHz (192 kHz digital IO only) 11 = reserved 8:7 LRCLK frame sync frequency (master mode) 00 = 48 kHz 01 = 96 kHz 10 = 192 kHz 11 = reserved 6 Frame sync type 0 = LRCLK 1 = pulse 5 TDM enable 0 = serial data out 1 = TDM out 4:2 MSB position 000 = delay by 1 001 = delay by 0 010 = delay by 8 011 = delay by 12 100 = delay by 16 All others are reserved 1:0 Output Word length 00 = 24 bits 01 = 20 bits 10 = 16 bits 11 = 16 bits
Table 33. SRC Serial Port Control Register (8 Bits)
Register Address 0x1056 Default = 0x00 Register Bits Function 7 Reserved (set to 0) 6:5 SRC serial input port select 00 = SDIN3 01 = SDIN2 10 = SDIN1 11 = SDIN0 4 LRCLK polarity 0 = left low, right high 1 = left high, right low 3 BCLK polarity 0 = data changes on falling edge 1 = data changes on rising edge 2:0 Serial input mode 000 = I2S 001 = left-justified 010 = reserved 011 = right-justified, 24 bits 100 = right-justified, 20 bits 101 = right-justified, 18 bits 110 = right-justified, 16 bits All others are reserved
Rev. 0 | Page 29 of 36
ADAV400
Table 34. ADC Input Mux Control Register
Register Address 0x1057 Default = 0x0001 Register Bits Function 15:4 Reserved (set to 0) 3 AIN4 to ADC 2 AIN3 to ADC 1 AIN2 to ADC 0 AIN1 to ADC
Table 37. User Control Register 1
Register Address 0x1059 Default Readback = 0x1E00 Register Bits Function 15:13 Reserved (set to 0) 12:9 Reserved (set to 0) These bits read back as 0b1111 8 SRC mux enable 0 = disabled 1 = enabled 7 SRC lock indicator (read only) 0 = SRC not locked 1 = SRC locked 6 MCLKO pin Enable 0 = MCLKO pin disabled 1 = MCLKO pin enabled 5:3 MCLKO select 000 = reserved 001 = 1024 x fS (49.152 MHz) 010 = reserved 011 = reserved 1xx = 128 x fS (6.144 MHz) 2:1 PLL Clock Select 00 = 64 x fS (3.072 MHz) 01 = 128 x fS (6.144 MHz) 10 = 256 x fS (12.288 MHz) 11 = 512 x fS (24.576 MHz) 0 PLL Enable 0 = PLL bypassed 1 = PLL in use
Table 35. Power Control Register
Register Address 0x1058 Default = 0x0000 Register Bits Function1 15 PLL 14 Reference buffer 13 ADC 12 VOUT4 DAC 11 VOUT3 DAC 10 VOUT2 DAC 9 VOUT1 DAC 8 AUX2 right DAC 7 AUX2 left DAC 6 AUX1/HP right DAC 5 AUX1/HP left DAC 4 Headphone amplifier right 3 Headphone amplifier left 2 SRC 1 Digital ADC and DAC engine 0 Audio processor
1
0 = powered down, 1 = powered up.
Table 38. DAC Amplifier Register Table 36. User Control Register 2
Register Address 0x105A Default = 0x0000 Register Bits Function 15:8 Reserved (set to 0) 7 Headphone amplifier mute 0 = normal operation 1 = mute 6:5 Reserved (set to 0) 4:0 Headphone amplifier attenuation 00000 = 0 dB 00001 = -1.5 dB 00010 = -3.0 dB .... ..... 11110 = -45.0 dB 11111 = -46.5 dB Register Address 0x110D Default = 0x0000 Register Bits Function 15:5 Reserved (set to 0) 4 DAC amplifier chopping1 0 = enabled 1 = disabled 3:0 Reserved (set to 0)
1
Set this bit to 1 to obtain maximum performance from the DAC amplifier.
Table 39. Headphone Amplifier Register
Register Address 0x1113 Default = 0x0000 Register Bits Function 15:1 Reserved (set to 0) 0 Headphone amplifier chopping1 0 = enabled 1 = disabled
1
Set this bit to 1 to obtain maximum performance from the DAC amplifier.
Rev. 0 | Page 30 of 36
ADAV400
AUDIO CORE CONTROL REGISTER
The bits in this register control the operation of the DSP core of the ADAV400 (see Table 29).
Zero Serial Input Port (Bit 6)
When this bit is set to 1, all input channels to the DSP core are forced to all 0s, effectively muting the output.
Enable SDO2 and SDO3 (Bit 14)
This bit is set to 1 by default and can be used to disable SDO2 and SDO3 if required.
Initiate Safe Transfer to Target RAM (Bit 5)
Setting this bit to 1 initiates a safeload transfer to the target/slew RAM. This bit clears when the operation is complete. Of five safeload register pairs (address/data), only those registers that have been written since the last safeload event occurred are transferred. Address 0 corresponds to the first target RAM location.
Slew RAM Muted (Bit 13)
This bit is set to 1 when the slew RAM mute operation has been completed. This bit is read-only and is automatically cleared by reading.
Initiate Safe Transfer to Parameter RAM (Bit 4)
Setting this bit to 1 initiates a safeload transfer to the parameter RAM. This bit clears when the operation is complete. Of five safeload registers pairs (address/data), only those registers that have been written since the last safeload event occurred are transferred. Address 0 corresponds to the first parameter RAM location.
Write Zero to Target RAM (Bit 12)
Setting this bit to 1 is equivalent to writing 0s to all locations in the target RAM. This effectively mutes any slew RAMs, such as volume controls used in a signal flow. To enable normal operation, clear this bit to 0.
Clear Registers to All Zeros (Bit 9)
Setting this bit to 0 sets the contents of the accumulators and serial output registers to 0. This bit defaults to 0; therefore, the ADAV400 powers up in clear mode and does not pass signals until a 1 is written to this bit. This is intended to prevent noises from inadvertently occurring during the power-up sequence.
Program Length (Bits [1:0]) 96 kHz and 192 kHz Modes
These bits set the length of the internal program. The default program length is 2560 instructions for fS = 48 kHz, but the program length can be shortened by factors of 2 to accommodate sample rates higher than 48 kHz. For fS = 96 kHz, set the program length to 1280 (01), and for fS = 192 kHz, set the length to 640 steps (10). Note that this is only valid for digital inputs and outputs.
Force Multiplier to Zero (Bit 8)
When this bit is set to 1, the input to the DSP multiplier is set to 0, which results in the multiplier output being 0. This control bit is included for maximum flexibility and is normally not used.
Initialize Data Memory with Zeros (Bit 7)
Setting this bit to 1 initializes all data memory locations to 0. This bit is cleared to 0 after the operation is complete. Assert this bit after a complete program/parameter download has occurred to ensure click-free operation.
Rev. 0 | Page 31 of 36
ADAV400
RAM MODULO CONTROL REGISTER
The ADAV400 uses a modulo RAM addressing scheme that allows very efficient coding of filters and other blocks by automatically incrementing the data RAM pointer at the end of each sample period. This works well for most audio applications that involve filtering. However, in some cases auto-incrementing the data RAM pointer is undesirable--for example, when it is required to store a word in data RAM and then access it in a subsequent audio sample period. For this reason, the data RAM in the ADAV400 can be partitioned into modulo and nonmodulo blocks by programming the RAM modulo control register (see Table 30). This register is programmed with the size of the modulo block required in blocks of 512 words, up to the maximum data RAM size of 20,480 words, which is the default setting of the register. For example, if the register is programmed with the value 0x2, the modulo RAM is 1024 (2 x 512) words starting from Address 0 to Address 1023, and the nonmodulo RAM is 19,456 words starting from Address 1024. This is not currently used in any of the library blocks within the development tool; however, it is included for maximum flexibility for custom software development.
Frame Sync Type (Bit 6)
This bit sets the type of signal on the LRCLK1 pin. When this bit is set to 0, the signal is a word clock with a 50% duty cycle; when this bit is set to 1, the signal is a pulse with a duration of one BCLK at the beginning of the data frame.
TDM Enable (Bit 5)
Setting this bit to 1 changes the output port from multiple serial outputs to a single TDM output stream available on SDO0. This bit must be set in both serial output control registers to enable 16-channel TDM on SDO0.
MSB Position (Bits [4:2])
These three bits set the position of the MSB of the data with respect to the LRCLK edge. The data outputs of the ADAV400 are always MSB-first.
Output Word Length (Bits [1:0])
These bits set the word length of the output data-word. All bits following the LSB are set to 0.
SERIAL INPUT CONTROL REGISTER
TDM Input Mode(Bit 5)
This bits selects either 8-channel or 16-channel TDM mode.
SERIAL OUTPUT CONTROL REGISTERS
Dither Enable (Bit 15)
Setting this bit to 1 enables dither on the appropriate channels.
LRCLK Polarity (Bit 4)
When this bit is set to 0, the left channel data on SDINx is clocked in when LRCLK1 is low, and the right channel input data is clocked in when LRCLK1 is high. When this bit is set to 1, this sequence is reversed. In TDM mode, when this bit is set to 0, data is clocked on the next valid BCLK edge (polarity of BCLK is set in Bit 3 of this register) following a falling edge on LRCLK1. When this bit is set to 1 and running in TDM mode, the input data is valid on the BCLK edge following a rising edge on LRCLK1. The serial input port can also operate with LRCLK1 as a pulse, rather than a clock. In this case, the first edge of the pulse is used by the ADAV400 to start the data frame. When the polarity bit is set to 0, data is clocked in on the falling edge of LRCLK1; when this bit is set to 1, data is clocked in on the rising edge.
TDM Output Mode (Bit 14)
This bits selects either 8-channel or 16-channel TDM mode.
LRCLK Polarity (Bit 13)
When this bit is set to 0, the left channel data is clocked when LRCLK is low, and the right channel data is clocked when LRCLK is high. When this bit is set to 1, this sequence is reversed.
BCLK Polarity (Bit 12)
This bit controls on which edge of the bit clock the output data is clocked. Data changes on the falling edge of BCLK1 when this bit is set to 0, and on the rising edge when this bit is set to 1.
Master/Slave (Bit 11)
This bit determines whether the output port is a clock master or slave. The default setting is slave; on power-up, Pin BCLK1 and Pin LRCLK1 are set as inputs until this bit is set to 1, at which time they become clock outputs.
BCLK Polarity (Bit 3)
This bit controls on which edge of the bit clock the input data changes, and on which edge it is clocked. Data changes on the falling edge of BCLK1 when this bit is set to 0, and on the rising edge when this bit is set at 1.
BCLK Frequency (Bits [10:9])
When the serial output port is a master, these bits set the frequency of the output bit clock, BCLK1.
Serial Input Mode (Bits [2:0])
These two bits control the data format that the input port expects to receive. It should be noted that Bit 3 and Bit 4 of the serial input control register will override these settings, so Bits 4 to Bit 0 must be set for correct operation. Refer to Figure 31, Figure 32, Figure 33, and Figure 34 for details on the different modes.
Frame Sync Frequency (Bits [8:7])
When the output port is a master, these bits set the frequency of the output word clock on the LRCLK1
Rev. 0 | Page 32 of 36
ADAV400
Table 27 can also be used to verify register settings for each serial data format.
Headphone Amplifier Attenuation (Bits [4:0])
These bits set the analog gain of the headphone amplifier. It can be set in steps of -1.5 dB from 0 dB to -46.5 dB.
SRC SERIAL PORT CONTROL REGISTER
SRC Serial Input Port Select (Bits [6:5])
These bits select which of the four serial data inputs are directed to the SRC
USER CONTROL REGISTER 1
SRC Mux Enable (Bit 8)
When this bit is set to 1, the SRC mux is enabled, passing the input selected by the SRC serial port control register to the SRC block, the output of which is then available to the DSP core. It also masks the selected serial data input as a direct input to the DSP core. See Figure 36 for more details on the SRC input configuration.
LRCLK0 BCLK0 REG: 0x1056 BITS [6:5] REG: 0x1058 BIT 2 SRC PU AUDIO PROCESSOR CORE
LRCLK Polarity (Bit 4)
When this bit is set to 0, the left channel data on the selected channel is clocked in when LRCLK0 is low, and the right channel input data is clocked in when LRCLK1 is high. When this bit is set to 1, this sequence is reversed.
BCLK Polarity (Bit 3)
This bit controls on which edge of the bit clock the input data changes, and on which edge it is clocked. Data changes on the falling edge of BCLK0 when this bit is set to 0, and on the rising edge when this bit is set to 1.
Serial Input Mode (Bits [2:0])
These two bits control the data format that the input port expects to receive. It should be noted that Bit 3 and Bit 4 of the serial input control register will override these settings, so Bits 4 to Bit 0 must be set for correct operation. Refer to Figure 31, Figure 32, Figure 33, and Figure 34 for details on the different modes. Table 27 can also be used to verify register settings for each serial data format. Note that TDM is not supported on the SRC.
MULTICHANNEL DIGITAL INPUTS
Figure 36. SRC Input Configuration
SRC Lock Indicator (Bit 7)
This bit is read only and indicates when the SRC is locked.
MCLKO Pin Enable (Bit 6)
With this bit set to 1, MCLKO is enabled and outputs the frequency selected by Bit 5 to Bit 3 in this register.
ADC INPUT MUX REGISTER
ADC Input Mux (Bits [3:0])
These bits are used to select which of the analog inputs are directed to the ADC. It is recommended that only one channel is selected at any time.
MCLKO Select (Bits [5:3])
These bits select the MCLKO frequency. All reserved settings are test modes and are not valid audio clocks.
PLL Clock Select (Bits [2:0])
These bits must be programmed to select the master clock, MCLKI, input frequency that is being used. For example, the default case is 64 x fS (3.072 MHz), which means that BCLKx can also be used as the MCLKI.
POWER CONTROL REGISTER
Power Control (Bits [15:0])
These bits can individually power up or power down the different blocks of the ADAV400.
USER CONTROL REGISTER 2
Headphone Amplifier Mute (Bit 7)
When set, this bit mutes the analog headphone amplifier.
DAC AMPLIFIER REGISTER
DAC Amplifier Chopping (Bit 4)
This bit should be set to 1 to ensure best performance on the headphone outputs.
Rev. 0 | Page 33 of 36
05811-017
SDIN0 SDIN1 SDIN2 SDIN3
ADAV400
TYPICAL APPLICATION DIAGRAM
3.3V 100nF 47F 100nF 47F 100nF 47F 100nF 10F + 100nF 3.3V
600Z 47F 100nF 47F
FZT953 47F 47F 100nF 47F + 100nF
+
+
+
+
+
+
+
ODVDD
VDRIVE
AVDD2
AVDD1
AVDD3
AVDD4
AVDD5
DVDD
DVDD
VOUT1
600Z VIN1L
47F + 20k 100nF
47F + 560 5.6nF
VOUT1
AINL1
VOUT4 600Z VIN4R 47F + 20k 100nF AUXL1 BCLK0 LRCLK0 BCLK1 LRCLK1 SDIN0 SDIN1 SDIN2 SDIN3 SDO0 SDO1 SDO2 SDO3 RESET CIRCUITRY CLOCK AUXR2 AINR4
47F + 560 5.6nF 47F + 560 5.6nF 47F + 560 5.6nF 100F + 10k
VOUT4
AUXL1
AUXR2
TO AUDIO CONTROLLER
600Z HPOUTL 470pF 600Z HPOUTR 10k 470pF
HPOUTL
ADAV400
HPOUTR IDAC 100F +
20k AVDD2 100nF 2k 1nF
RESET PLL_LF VREF
MCLKI
I2 C CONTROLLER
SDA SCL AD0 FILTA
100nF
+
47F
100nF
+
47F
05811-036
DGND
DGND
DGND
DGND
DGND
AGND
AGND
AGND
AGND
AGND
DGND
FILTD 100nF
+
47F
Figure 37. Typical Application Circuit
Rev. 0 | Page 34 of 36
ADAV400 OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
80 1 PIN 1
16.20 16.00 SQ 15.80
61 60
TOP VIEW (PINS DOWN)
14.20 14.00 SQ 13.80
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.10 MAX COPLANARITY
20 21 40
41
VIEW A
ROTATED 90 CCW
VIEW A
0.65 BSC LEAD PITCH
0.38 0.32 0.22
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 38. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADAV400KSTZ 2 ADAV400KSTZ-REEL2 EVAL-ADAV400EB
1
Temperature Range 0C to 70C 0C to 70C
Package Description 80-Lead Low Profile Quad Flat Package [LQFP] 80-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board
Package Option ST-80-2 ST-80-2
The ADAV400 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and can withstand surface-mount soldering at up to 255C (5C). In addition, it is backward-compatible with conventional Sn/Pb soldering processes. This means the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220C to 235C. 2 Z = Pb-free part.
Rev. 0 | Page 35 of 36
ADAV400 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05811-0-1/06(0)
Rev. 0 | Page 36 of 36

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